View ICS9250YF-30-T_3752463.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

integrated circuit systems, inc. ics9250-30 0398a?07/03/02 block diagram pin configuration recommended application: 810/810e and solano type chipset output features: 2 - cpus @ 2.5v, up to 200mhz. 13 - sdram @ 3.3v, up to 200mhz. 3 - 3v66 @ 3.3v, 2x pci mhz. 8 - pci @3.3v. 1 - 48mhz, @3.3v fixed. 1 - 24/48mhz @ 3.3v 1 - ref @3.3v, 14.318mhz. 1 - ioapic @ 2.5v. features: support pc133 sdram. up to 200mhz frequency support support power management through pd#. spread spectrum for emi control ( 0.25% center spread or 0 to -0.5% down spread) uses external 14.318mhz crystal fs pins for frequency select key specifications: cpu output jitter: <250ps cpu output skew: <175ps pci output skew: <500ps 3v66 output skew <175ps for group skew timing, please refer to the group timing relationship table. frequency generator & integrated buffers for celeron & p ii / iii ? 56-pin 300 mil ssop 1. these pins will have 1.5 to 2x drive strength. * 120k ohm pull-up to vdd on indicated inputs. s data sclk pll2 pll1 spread spectrum 48mhz 24_48mhz cpuclk [1:0] 2 12 8 3 sdram [11:0] ioapic pciclk [7:0] sdram_f 3v66 [2:0] x1 x2 xtal osc cpu divder sdram divder ioapic divder pci divder 3v66 divder fs[4:0] pd# sel24_48# control logic config. reg. / 2 ref0 vddref x1 x2 gndref gnd3v66 3v66-1 3v66-2 vdd3v66 vddpci *fs0/pciclk0 *fs1/pciclk1 *sel24_48#/pciclk2 gndpci pciclk3 pciclk4 pciclk5 vddpci pciclk6 pciclk7 gndpci pd# sclk s data vddsdr sdram11 sdram10 gndsdr 3v66-0 1 1 1 ref0/fs4* vddlapic ioapic vddlcpu cpuclk0 cpuclk1 gndlcpu gndsdr sdram0 sdram1 sdram2 vddsdr sdram3 sdram4 sdram5 gndsdr sdram6 sdram7 sdram_f vddsdr gnd48 24_48mhz/fs2 * 48mhz/fs3* vdd48 vddsdr sdram8 sdram9 gndsdr 1 1 1 ics9250-30 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 fs4 fs3 fs2 fs1 fs0 cpu sdram 3v66 pci 0000066.67100.0066.6733.33 0001168.33102.5068.3334.17 0011080.00120.0080.0040.00 0011183.00124.5083.0041.50 01000 100.00 100.00 66.67 33.33 01011 103.00 103.00 68.67 34.33 01110 115.00 115.00 76.67 38.33 01111 200.00 200.00 66.67 33.33 10000 133.33 133.33 66.67 33.33 10001 166.67 166.67 83.34 41.67 10011 137.00 137.00 68.50 34.25 10111 160.00 160.00 80.00 40.00 11000 133.33 100.00 66.67 33.33 11001 166.67 125.00 83.34 41.67 11011 137.00 102.75 68.50 34.25 11111 160.00 120.00 80.00 40.00 functionality for other hardware/i 2 c selectable frequencies please refer to byte 0 frequency select register.
2 ics9250-30 0398a?07/03/02 general description pin configuration the ics9250-30 is a single chip clock solution for desktop designs using the 810/810e and solano style chipset. it provides all necessary clock signals for such a system. spread spectrum may be enabled through i 2 c programming. spread spectrum typically reduces system emi by 8db to 10db. this simplifies emi qualification without resorting to board design iterations or costly shielding. the ics9250- 30 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. serial programming i 2 c interface allows changing functions, stop clock programming and frequency selection. n i p r e b m u n e m a n n i pe p y tn o i t p i r c s e d , 8 1 , 0 1 , 9 , 1 , 7 3 , 3 3 , 2 3 , 5 2 5 4 d d vr w py l p p u s r e w o p v 3 . 3 21 xn i k c a b d e e f d n a ) f p 3 3 ( p a c d a o l l a n r e t n i s a h , t u p n i l a t s y r c 2 x m o r f r o t s i s e r 32 xt u o d a o l l a n r e t n i s a h . z h m 8 1 3 . 4 1 y l l a n i m o n , t u p t u o l a t s y r c ) f p 3 3 ( p a c , 1 2 , 4 1 , 5 , 4 , 6 3 , 9 2 , 8 2 9 4 , 1 4 d n gr w py l p p u s v 3 . 3 r o f s n i p d n u o r g 6 , 7 , 8] 0 : 2 [ 6 6 v 3t u ob u h r o f s t u p t u o k c o l c z h m 6 6 d e x i f v 3 . 3 1 1 0 k l c i c pt u os t u p t u o k c o l c i c p v 3 . 3 0 s fn i. n o r e w o p t a d e h c t a l t u p n i . t i b t c e l e s y c n e u q e r f t u p n i c i g o l 2 1 1 k l c i c pt u o. s t u p t u o k c o l c i c p v 3 . 3 1 s fn i. n o r e w o p t a d e h c t a l t u p n i . t i b t c e l e s y c n e u q e r f t u p n i c i g o l , 7 1 , 9 1 , 0 2 5 1 , 6 1 ] 3 : 7 [ k l c i c pt u o. s t u p t u o k c o l c i c p v 3 . 3 3 1 2 k l c i c pt u o. t u p t u o k c o l c i c p v 3 . 3 # 8 4 _ 4 2 l e sn i z h m 8 4 = 5 3 n i p d e t c e l e s s i " 0 " c i g o l n e h w . t c e l e s c i g o l t u p n i . z h m 4 2 = 5 3 n i p d e t c e l e s s i " 1 " c i g o l n e h w 2 2# d pn i e h t n w o d r e w o p o t d e s u n i p t u p n i w o l e v i t c a s u o n o r h c n y s a d e l b a s i d e r a s k c o l c l a n r e t n i e h t . e t a t s r e w o p w o l a o t n i e c i v e d e h t f o y c n e t a l e h t . d e p p o t s e r a l a t s y r c e h t d n a o c v e h t d n a . s m 3 n a h t r e t a e r g e b t o n l l i w n w o d r e w o p 3 2k l c sn ii f o t u p n i k c o l c 2 . t u p n i l a i r e s c 4 2a t a d sn ii r o f t u p n i a t a d 2 . t u p n i l a i r e s c 4 3 z h m 8 4t u o. b s u r o f t u p t u o k c o l c z h m 8 4 d e x i f v 3 . 3 3 s fn i. n o r e w o p t a d e h c t a l t u p n i . t i b t c e l e s y c n e u q e r f t u p n i c i g o l 5 3 2 s fn i. n o r e w o p t a d e h c t a l t u p n i . t i b t c e l e s y c n e u q e r f t u p n i c i g o l z h m 8 4 _ 4 2t u o. t u p t u o z h m 8 4 r o 4 2 v 3 . 3 8 3f _ m a r d st u oi y b d e t c e f f a t o n m a r d s z h m 0 0 1 g n i n n u r e e r f v 3 . 3 2 c , 4 4 , 6 4 , 7 4 , 8 4 , 9 3 , 0 4 , 2 4 , 3 4 6 2 , 7 2 , 0 3 , 1 3 ] 0 : 1 1 [ m a r d st u o f f o d e n r u t e b n a c s t u p t u o m a r d s l l a . t u p t u o m a r d s v 3 . 3 i h g u o r h t 2 . c 0 5l d n gr w p. c i p a & u p c r o f y l p p u s r e w o p v 5 . 2 r o f d n u o r g 2 5 , 1 5] 0 : 1 [ k l c u p ct u o s f m o r f d e v i r e d y c n e u q e r f t u p t u o . t u p t u o k c o l c s u b t s o h v 5 . 2 . s n i p 5 5 , 3 5l d d vr w p. c i p a o i , u p c r o f y l p p y u s r e w o p v 5 . 2 4 5c i p a o it u o. z h m 7 6 . 6 1 t a g n i n n u r s t u p t u o k c o l c v 5 . 2 6 5 4 s fn i. n o r e w o p t a d e h c t a l t u p n i . t i b t c e l e s y c n e u q e r f t u p n i c i g o l 0 f e rt u o. t u p t u o k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 , v 3 . 3
3 ics9250-30 0398a?07/03/02 byte 0: functionality and frequency select register (default=0) (1 = enable, 0 = disable) notes: 1. default at power-up will be for latched logic inputs to define frequency, as displayed by bit 3. 2. the i 2 c readback for bit 2, 7:4 indicate the revision code. t i bn o i t p i r c s e dd w p t i b ) 4 : 7 , 2 ( 2 t i b 7 t i b6 t i b5 t i b4 t i b k l c u p c z h m m a r d s z h m 6 6 v 3 z h m k l c i c p c i p a o i z h m e g a t n e c e r p d a e r p s 1 0 0 0 0 1 e t o n 4 s f 3 s f2 s f1 s f0 s f 00000 7 6 . 6 60 0 . 0 0 17 6 . 6 63 3 . 3 37 6 . 6 1d a e r p s n w o d % 5 . 0 - o t 0 00001 0 0 . 0 60 0 . 0 90 0 . 0 60 0 . 0 30 0 . 5 1d a e r p s r e t n e c % 5 2 . 0 - / + 00010 0 8 . 6 60 2 . 0 0 10 8 . 6 60 4 . 3 30 7 . 6 1d a e r p s r e t n e c % 5 2 . 0 - / + 00011 3 3 . 8 60 5 . 2 0 13 3 . 8 67 1 . 4 38 0 . 7 1d a e r p s r e t n e c % 5 2 . 0 - / + 00100 0 0 . 0 70 0 . 5 0 10 0 . 0 70 0 . 5 30 5 . 7 1d a e r p s r e t n e c % 5 2 . 0 - / + 00101 0 0 . 5 70 5 . 2 1 10 0 . 5 70 5 . 7 35 7 . 8 1d a e r p s r e t n e c % 5 2 . 0 - / + 00110 0 0 . 0 80 0 . 0 2 10 0 . 0 80 0 . 0 40 0 . 0 2d a e r p s r e t n e c % 5 2 . 0 - / + 00111 0 0 . 3 80 5 . 4 2 10 0 . 3 80 5 . 1 45 7 . 0 2d a e r p s r e t n e c % 5 2 . 0 - / + 01000 0 0 . 0 0 10 0 . 0 0 17 6 . 6 63 3 . 3 37 6 . 6 1d a e r p s n w o d % 5 . 0 - o t 0 01001 0 0 . 0 90 0 . 0 90 0 . 0 60 0 . 0 30 0 . 5 1d a e r p s r e t n e c % 5 2 . 0 - / + 01010 0 3 . 0 0 10 3 . 0 0 17 8 . 6 63 4 . 3 32 7 . 6 1d a e r p s r e t n e c % 5 2 . 0 - / + 01011 0 0 . 3 0 10 0 . 3 0 17 6 . 8 63 3 . 4 37 1 . 7 1d a e r p s r e t n e c % 5 2 . 0 - / + 01100 0 0 . 5 0 10 0 . 5 0 10 0 . 0 70 0 . 5 30 5 . 7 1d a e r p s r e t n e c % 5 2 . 0 - / + 01101 0 0 . 0 1 10 0 . 0 1 13 3 . 3 77 6 . 6 33 3 . 8 1d a e r p s r e t n e c % 5 2 . 0 - / + 01110 0 0 . 5 1 10 0 . 5 1 17 6 . 6 73 3 . 8 37 1 . 9 1d a e r p s r e t n e c % 5 2 . 0 - / + 01111 0 0 . 0 0 20 0 . 0 0 27 6 . 6 63 3 . 3 37 6 . 6 1d a e r p s r e t n e c % 5 2 . 0 - / + 10000 3 3 . 3 3 13 3 . 3 3 17 6 . 6 63 3 . 3 37 6 . 6 1d a e r p s n w o d % 5 . 0 - o t 0 10001 7 6 . 6 6 17 6 . 6 6 14 3 . 3 87 6 . 1 43 8 . 0 2d a e r p s r e t n e c % 5 2 . 0 - / + 10010 0 7 . 3 3 10 7 . 3 3 15 8 . 6 63 4 . 3 31 7 . 6 1d a e r p s r e t n e c % 5 2 . 0 - / + 10011 0 0 . 7 3 10 0 . 7 3 10 5 . 8 65 2 . 4 33 1 . 7 1d a e r p s r e t n e c % 5 2 . 0 - / + 10100 0 0 . 0 4 10 0 . 0 4 10 0 . 0 70 0 . 5 30 5 . 7 1d a e r p s r e t n e c % 5 2 . 0 - / + 10101 0 0 . 5 4 10 0 . 5 4 10 5 . 2 75 2 . 6 33 1 . 8 1d a e r p s r e t n e c % 5 2 . 0 - / + 10110 0 0 . 0 5 10 0 . 0 5 10 0 . 5 70 5 . 7 35 7 . 8 1d a e r p s r e t n e c % 5 2 . 0 - / + 10111 0 0 . 0 6 10 0 . 0 6 10 0 . 0 80 0 . 0 40 0 . 0 2d a e r p s r e t n e c % 5 2 . 0 - / + 11000 3 3 . 3 3 10 0 . 0 0 17 6 . 6 63 3 . 3 37 6 . 6 1d a e r p s n w o d % 5 . 0 - o t 0 11001 7 6 . 6 6 10 0 . 5 2 14 3 . 3 87 6 . 1 43 8 . 0 2d a e r p s r e t n e c % 5 2 . 0 - / + 11010 0 7 . 3 3 18 2 . 0 0 15 8 . 6 63 4 . 3 31 7 . 6 1d a e r p s r e t n e c % 5 2 . 0 - / + 11011 0 0 . 7 3 15 7 . 2 0 10 5 . 8 65 2 . 4 33 1 . 7 1d a e r p s r e t n e c % 5 2 . 0 - / + 11100 0 0 . 0 4 10 0 . 5 0 10 0 . 0 70 0 . 5 30 5 . 7 1d a e r p s r e t n e c % 5 2 . 0 - / + 11101 0 0 . 5 4 15 7 . 8 0 10 5 . 2 75 2 . 6 33 1 . 8 1d a e r p s r e t n e c % 5 2 . 0 - / + 11110 0 0 . 0 5 10 5 . 2 1 10 0 . 5 70 5 . 7 35 7 . 8 1d a e r p s r e t n e c % 5 2 . 0 - / + 11111 0 0 . 0 6 10 0 . 0 2 10 0 . 0 80 0 . 0 40 0 . 0 2d a e r p s r e t n e c % 5 2 . 0 - / + 3 t i b s t u p n i d e h c t a l , t c e l e s e r a w d r a h y b d e t c e l e s s i y c n e u q e r f - 0 4 : 7 , 2 t i b y b d e t c e l e s s i y c n e u q e r f - 1 0 1 t i b l a m r o n - 0 e l b a n e m u r t c e p s d a e r p s - 1 1 0 t i b g n i n n u r - 0 s t u p t u o l l a e t a t s i r t - 1 0
4 ics9250-30 0398a?07/03/02 byte 1: control register (1 = enable, 0 = disable) notes: 1. inactive means outputs are held low and are disabled from switching. these outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. pwd = power on default t i b# n i pd w pn o i t p i r c s e d 7 t i b-x # 3 s f 6 t i b-x # 0 s f 5 t i b-x # 2 s f 4 t i b5 30 # z h m 8 4 _ 4 2 3 t i b-1 ) d e v r e s e r ( 2 t i b4 31 z h m 8 4 1 t i b-1 ) d e v r e s e r ( 0 t i b8 31 f _ m a r d s t i b# n i pd w pn o i t p i r c s e d 7 t i b0 21 7 k l c i c p 6 t i b9 11 6 k l c i c p 5 t i b7 11 5 k l c i c p 4 t i b6 11 4 k l c i c p 3 t i b5 11 3 k l c i c p 2 t i b3 1 1 2 k l c i c p 1 t i b2 11 1 k l c i c p 0 t i b1 11 0 k l c i c p byte 3: control register (1 = enable, 0 = disable) byte 2: control register (1 = enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b9 31 7 m a r d s 6 t i b0 41 6 m a r d s 5 t i b2 41 5 m a r d s 4 t i b3 41 4 m a r d s 3 t i b4 41 3 m a r d s 2 t i b6 4 1 2 m a r d s 1 t i b7 41 1 m a r d s 0 t i b8 41 0 m a r d s t i b# n i pd w pn o i t p i r c s e d 7 t i b81 2 _ 6 6 v 3 6 t i b61 0 _ 6 6 v 3 5 t i b71 1 _ 6 6 v 3 4 t i b-x # 4 s f 3 t i b4 51 c i p a o i 2 t i b-x # 1 s f 1 t i b1 51 1 k l c u p c 0 t i b2 51 0 k l c u p c byte 4: control register (1 = enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) d e v r e s e r ( 6 t i b-1 ) d e v r e s e r ( 5 t i b-1 ) d e v r e s e r ( 4 t i b-x # z h m 8 4 _ 4 2 3 t i b6 21 1 1 m a r d s 2 t i b7 21 0 1 m a r d s 1 t i b0 31 9 m a r d s 0 t i b1 31 8 m a r d s byte 5: control register (1 = enable, 0 = disable) byte 6: peripheral , active/inactive register (1= enable, 0 = disable) note: don?t write into this register, writing into this register can cause malfunction t i b# n i pd w pn o i t p i r c s e d 7 t i b-0 ) e t o n ( d e v r e s e r 6 t i b-0 ) e t o n ( d e v r e s e r 5 t i b-0 ) e t o n ( d e v r e s e r 4 t i b-0 ) e t o n ( d e v r e s e r 3 t i b-0 ) e t o n ( d e v r e s e r 2 t i b-1 ) e t o n ( d e v r e s e r 1 t i b-1 ) e t o n ( d e v r e s e r 0 t i b-0 ) e t o n ( d e v r e s e r
5 ics9250-30 0398a?07/03/02 absolute maximum ratings stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. core supply voltage . . . . . . . . . . . . . . . . . . . . 4.6 v i/o supply voltage . . . . . . . . . . . . . . . . . . . . . 3.6v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . ?65c to +150c case temperature . . . . . . . . . . . . . . . . . . . . . . 115c electrical characteristics - input / supply / common output parameters t a = 0 - 70o c; supply voltage v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2 v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd -5 5 input low current i il1 v in = 0 v; inputs with no pull-up resistors -5 input low current i il2 v in = 0 v; inputs with pull-up resistors -200 i dd3.3op cl = max cap loads; select @ 66mhz 350 400 i ddl2.5op cl = max cap loads; select @ 66mhz 13 20 power down current i dd3.3pd cl = 0 pf; with input to vdd or gnd 275 600 a input frequency f i v dd = 3.3 v 14.32 mhz pin inductance l p in 7nh c in logic inputs 5 pf c out output pin capacitance 6 pf c inx x1 & x2 pins 27 45 pf transition time 1 t trans to 1st crossing of target freq. 3 ms settling time 1 t s from 1st crossing to 1% target freq. 3ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. 3ms t pzh, t pzl output enable delay(all outputs) 1 10 ns t phz, t plz output disable delay(all outputs) 1 10 ns 1 guaranteed by design, not 100% tested in production. a delay 1 input capacitance 1 ma operating supply current
6 ics9250-30 0398a?07/03/02 group timing relationship table 1 offset tolerance offset tolerance offset tolerance offset tolerance cpu to sdram 2.5ns 500ps 5.0ns 500ps 0.0ns 500ps 3.75ns 500ps cpu to 3v66 7.5ns 500ps 5.0ns 500ps 0.0ns 500ps 0.0ns 500ps sdram to 3v66 0.0ns 500ps 0.0ns 500ps 0.0ns 500ps 3.75ns 500ps 3v66 to pci 1.5-3.5ns 500ps 1.5-3.5ns 500ps 1.5-3.5ns 500ps 1.5-3.5ns 500ps pci to ioapic 0.0ns 1.0ns 0.0ns 1.0ns 0.0ns 1.0ns 0.0ns 1.0ns usb & dot async n/a async n/a async n/a async n/a 1 guaranteed by design, not 100% tested in production. cpu 133mhz sdram 100mhz sdram 100mhz sdram 100mhz sdram 133mhz group cpu 66mhz cpu 100mhz cpu 133mhz electrical characteristics - cpu t a = 0 - 70c; v ddl = 2.5 v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance 1 r dsp2b v o = v dd *(0.5) 13.5 22 45 ? output impedance 1 r dsn2b v o = v dd *(0.5) 13.5 23 45 ? output high voltage v oh2b i oh = -1 ma 2 v output low voltage v ol2b i ol = 1 ma 0.4 v v oh @ min = 1.0 v -27 -68 v oh @ max = 2.375 v -9 -27 v ol @ min = 1.2 v 27 54 v ol @ max = 0.3 v 11 30 rise time 1 t r2b v ol = 0.4 v, v oh = 2.0 v 0.4 1.2 1.6 ns fall time 1 t f2b v oh = 2.0 v, v ol = 0.4 v 0.4 1.2 1.6 ns dut y c y cle 1 d t2b v t = 1.25 v, 66, 100 mhz 45 50 55 % skew window 1 t sk2b v t = 1.25 v 57 175 ps jitter, cycle-to-cycle 1 t jcyc-cyc2b v t = 1.25 v 120 250 ps 1 guaranteed by design, not 100% tested in production. ma output low current i ol2b ma output high current i oh2b
7 ics9250-30 0398a?07/03/02 electrical characteristics - 3v66 t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance r dsp1 1 v o = v dd *(0.5) 12 17 55 ? output impedance r dsn1 1 v o = v dd *(0.5) 12 18 55 ? output high voltage v oh1 i oh = -1 ma 2.4 v output low voltage v ol1 i ol = 1 ma 0.55 v v oh @ min = 1.0 v -33 -108 v oh @ max = 3.135 v -9 -33 v ol @ min = 1.95 v 30 95 v ol @ max = 0.4 v 29 38 rise time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 0.4 1 1.6 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 0.4 1 1.6 ns dut y c y cle 1 d t1 v t = 1.5 v 45 50 55 % skew window 1 t sk1 v t = 1.5 v 75 175 ps jitter, cycle-to-cycle 1 t jcyc-cyc1 v t = 1.5 v 155 500 ps 1 guaranteed by design, not 100% tested in production. output high current i oh1 ma output low current i ol1 ma electrical characteristics - ioapic t a = 0 - 70c; v ddl = 2.5 v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance 1 r dsp4b v o = v dd *(0.5) 9 21.5 30 w output impedance 1 r dsn4b v o = v dd *(0.5) 9 23 30 w output high voltage v oh4b i oh = -1 ma 2 v output low voltage v ol4b i ol = 1 ma 0.4 v v oh @ min = 1.0 v -27 -68 v oh @ max = 2.375 v -9 -27 v ol @ min = 1.2 v 27 54 v ol @ max = 0.3 v 11 30 rise time 1 t r4b v ol = 0.4 v, v oh = 2.0 v 0.4 1.2 1.6 ns fall time 1 t f4b v oh = 2.0 v, v ol = 0.4 v 0.4 1.3 1.6 ns duty cycle 1 d t4b v t = 1.25 v 45 50.6 55 % jitter, cycle-to-cycle 1 t jcyc-cyc4b v t = 1.25 v 210 500 ps 1 guaranteed by design, not 100% tested in production. output high current i oh4b ma output low current i ol4b ma
8 ics9250-30 0398a?07/03/02 electrical characteristics - sdram t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 20-30 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance 1 r dsp3 v o = v dd *(0.5) 10 14 24 ? output impedance 1 r dsn3 v o = v dd *(0.5) 10 18 24 ? output high voltage v oh3 i oh = -1 ma 2.4 v output low voltage v ol3 i ol = 1 ma 0.4 v v oh @ min = 2.0 v -54 -92 v oh @ max = 3.135 v -16 -46 v ol @ min = 1.0 v 54 68 v ol @ max = 0.4 v 29 53 rise time 1 t r3 v ol = 0.4 v, v oh = 2.4 v 0.4 1 1.6 ns fall time 1 t f3 v oh = 2.4 v, v ol = 0.4 v 0.4 1.5 1.6 ns duty cycle 1 d t3 v t = 1.5 v 45 52.5 55 % skew window 1 t sk3 v t = 1.5 v 58 250 ps 1 guaranteed by design, not 100% tested in production. 170 250 ps jitter, cycle-to-cycle 1 t jcyc-cyc3 v t = 1.5 v, 66, 100 mhz output high current i oh3 ma output low current i ol3 ma parameter symbol conditions min typ max units output impedance 1 r dsp1 v o = v dd *(0.5) 12 14 55 ? output impedance 1 r dsn1 v o = v dd *(0.5) 12 18 55 ? output high voltage v oh1 i oh = -1 ma 2.4 v output low voltage v ol1 i ol = 1 ma 0.55 v v oh @ min = 1.0 v -33 -106 v oh @ max = 3.135 v -14 -33 v ol @ min = 1.95 v 30 94 v ol @ max = 0.4 v 29 38 rise time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 0.5 1.5 2 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 0.5 1.6 2 ns duty cycle 1 d t1 v t = 1.5 v 45 51.9 55 % skew window 1 t sk1 v t = 1.5 v 328 500 ps jitter, cycle-to-cycle 1 t jcyc-cyc1 v t = 1.5 v 170 500 ps 1 guaranteed by design, not 100% tested in production. t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-30 pf (unless otherwise specified) electrical characteristics - pci output high current i oh1 ma output low current i ol1 ma
9 ics9250-30 0398a?07/03/02 electrical characteristics - ref, 24,48mhz t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance 1 r dsp5 v o = v dd *(0.5) 12 17 55 ? output impedance 1 r dsn5 v o = v dd *(0.5) 12 18 55 ? output high voltage v oh15 i oh = -1 ma 2.4 v output low voltage v ol5 i ol = 1 ma 0.55 v v oh @ min = 1.0 v -33 -108 v oh @ max = 3.135 v -9 -33 v ol @ min = 1.95 v 30 95 v ol @ max = 0.4 v 29 38 rise time 1 t r5 v ol = 0.4 v, v oh = 2.4 v 0.4 1.2 4 ns fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v 0.4 1.2 4 ns dut y c y cle 1 d t5 v t = 1.5 v 455255 % jitter, cycle-to-cycle 1 t j c y c-c y c5 v t = 1.5 v, fixed clocks 310 500 ps jitter, cycle-to-cycle 1 t jcyc-cyc5 v t = 1.5 v, ref clocks 720 1000 ps 1 guaranteed by design, not 100% tested in production. output high current i oh5 ma output low current i ol5 ma
10 ics9250-30 0398a?07/03/02 1. the ics clock generator is a slave/receiver, i 2 c component. it can read back the data stored in the latches for verification. read-back will support intel piix4 "block-read" protocol . 2. the data transfer rate supported by this clock generator is 100k bits/sec or less (standard mode) 3. the input is operating at 3.3v logic levels. 4. the data byte format is 8 bit bytes. 5. to simplify the clock generator i 2 c interface, the protocol is set to use only " block-writes " from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. 6. at power-on, all registers are set to a default condition, as shown. general i 2 c serial interface information the information in this section assumes familiarity with i 2 c programming. for more information, contact ics for an i 2 c programming application note. how to write: ? controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends a dummy command code ics clock will acknowledge controller (host) sends a dummy byte count ics clock will acknowledge controller (host) starts sending first byte (byte 0) through byte 5 ics clock will acknowledge each byte one at a time . controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the byte count controller (host) acknowledges ics clock sends first byte (byte 0) through byte 5 controller (host) will need to acknowledge each byte controller (host) will send a stop bit notes: controller (host) ics (slave/receiver) start bit address d3 (h) ack byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack stop bit how to read: controller (host) ics (slave/receiver) start bit address d2 (h) ack dummy command code ack dummy byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack stop bit how to write:
11 ics9250-30 0398a?07/03/02 fig. 1 shared pin operation - input/output pins the i/o pins designated by (input/output) on the ics9250- 30 serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm (10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent via to vdd clock trace to load series term. res. programming header via to gnd device pad 2k 8.2k operating period. figure 1 shows a means of implementing this function when a switch or 2 pin header is used. with no jumper is installed the pin will be pulled high. with the jumper in place the pin will be pulled low. if programmability is not necessary, than only a single resistor is necessary. the programming resistors should be located close to the series termination resistor to minimize the current loop area. it is more important to locate the series termination resistor close to the driver than the programming resistor.
12 ics9250-30 0398a?07/03/02 power down waveform note 1. after pd# is sampled active (low) for 2 consective rising edges of cpuclks, all the output clocks are driven low on their next high to low tranistiion. 2 . power-up latency <3ms. 3. waveform shown for 100mhz
13 ics9250-30 0398a?07/03/02 group offset waveforms cycle repeats 0ns cpu 66mhz cpu 100mhz cpu 133mhz sdram 133mhz sdram 100mhz 3.5v 66mhz pci 33mhz apic 33mhz ref 14.318mhz usb 48mhz 10ns 20ns 30ns 40ns
14 ics9250-30 0398a?07/03/02 general layout precautions: 1) use a ground plane on the top routing layer of the pcb in all areas not used by traces. 2) make all power traces and ground traces as wide as the via pad for lower inductance. component values: c1 : crystal load values determined by user c2 : 22f/20v/d case/tantalum avx tajd226m020r c3 : 15pf capacitor fb = fair-rite products 2512066017x1 all unmarked capacitors are 0.01f ceramic notes: 1 all clock outputs should have provisions for a 15pf capacitor between the clock output and series terminating resistor. not shown in all places to improve readability of diagram. 2 optional crystal load capacitors are recommended. they should be included in the layout but not inserted unless needed. connections to vdd: power groups: analog vddref = x1, x2 pll1 digital vddpci, vddsdr, vddlcpu, vddlapic
15 ics9250-30 0398a?07/03/02 ordering information ics9250 y f-30-t designation for tape and reel packaging pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics = standard device example: ics xxxx y f - ppp - t index area index area 12 1 2 n d h x 45 h x 45 e1 e seating plane seating plane a1 a e -c- - c - b .10 (.004) c .10 (.004) c c l 300 mil ssop package min max min max a 2.41 2.80 .095 .110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 d e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 l 0.50 1.02 .020 .040 n 0 8 0 8 min max min max 56 18.31 18.55 .720 .730 10-0034 reference doc.: jedec publication 95, mo-118 variations see variations see variations n d mm. d (inch) see variations see variations 0.635 basic 0.025 basic symbol in millimeters in inches common dimensions common dimensions

▲Up To Search▲

Price & Availability of ICS9250YF-30-T

	To Download ICS9250YF-30-T Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .